EZ80L92MCU Datasheet, PDF (130/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
115
UART Line Control Registers
This register is used to control the communication control parameters. See Tables 60 and
61.
Table 60. UART Line Control Registers (UART0_LCTL = 00C3h, UART1_LCTL =
00D3h)
Bit
Reset
CPU Access
Note: R/W = Read/Write.
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Bit
Position
7
DLAB
6
SB
5
FPE
4
EPS
Value
0
1
0
1
0
1
0
1
Description
Access to the UART registers at I/O addresses UARTx_RBR,
UARTx_THR, and UARTx_IER is enabled.
Access to the Baud Rate Generator registers at I/O addresses
UARTx_BRG_L and UARTx_BRG_H is enabled.
Do not send a BREAK signal.
Send Break
UART sends continuous zeroes on the transmit output from
the next bit boundary. The transmit data in the transmit shift
register is ignored. After forcing this bit High, the TxD output
is 0 only after the bit boundary is reached. Just before forcing
TxD to 0, the transmit FIFO is cleared. Any new data written
to the transmit FIFO during a break should be written only
after the THRE bit of UARTx_LSR register goes High. This
new data is transmitted after the UART recovers from the
break. After the break is removed, the UART recovers from
the break for the next BRG edge.
Do not force a parity error.
Force a parity error. When this bit and the party enable bit
(PEN) are both 1, an incorrect parity bit is transmitted with the
data byte.
Use odd parity for transmission. The total number of 1 bits in
the transmit data plus parity bit is odd.
Use even parity for transmission. The total number of 1 bits in
the transmit data plus parity bit is even.
PS013012-1004
P R E L I M I N A R Y Universal Asynchronous Receiver/Transmitter