EZ80L92MCU Datasheet, PDF (150/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
135
SPI Status Register
The SPI Status Read-Only register returns the status of data transmitted using the serial
peripheral interface. Reading the SPI_SR register clears Bits 7, 6, and 4 to a logical 0. See
Table 72.
Table 72. SPI Status Register (SPI_SR = 00BBh)
Bit
Reset
CPU Access
Note: R = Read Only.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Bit
Position
7
SPIF
6
WCOL
5
4
MODF
[3:0]
Value Description
0
SPI data transfer is not finished.
1
SPI data transfer is finished. If enabled, an interrupt is
generated. This bit flag is cleared to 0 by a Read of the
SPI_SR register.
0
An SPI write collision is not detected.
1
An SPI write collision is detected. This bit flag is cleared to 0
by a Read of the SPI_SR registers.
0
Reserved.
0
A mode fault (multimaster conflict) is not detected.
1
A mode fault (multimaster conflict) is detected. This bit flag is
cleared to 0 by a Read of the SPI_SR register.
0000 Reserved.
PS013012-1004
PRELIMINARY
Serial Peripheral Interface