EZ80L92MCU Datasheet, PDF (47/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
32
eZ80^® CPU Core
The eZ80^® CPU is the first 8-bit microprocessor to support 16 MB linear addressing. Each
software module or task under a real-time executive or operating system can operate in
Z80-compatible (64 KB) mode or full 24-bit (16 MB) address mode.
The eZ80^® CPU instruction set is a superset of the instruction sets for the Z80 and Z180
CPUs. Z80 and Z180 programs can be executed on an eZ80^® CPU with little or no modi-
fication.
Features
• Code-compatible with Z80 and Z180 products
• 24-bit linear address space
• Single-cycle instruction fetch
• Pipelined fetch, decode, and execute
• Dual Stack Pointers for ADL (24-bit) and Z80 (16-bit) memory modes
• 24-bit CPU registers and ALU (Arithmetic Logic Unit)
• Debug support
• Nonmaskable Interrupt (NMI), plus support for 128 maskable vectored interrupts
New and Improved Instructions
• Four new block transfer instructions provide DMA-like operations for memory to I/O
and I/O to memory transfers. These new instructions are:
– INDRX (input from I/O, decrement the memory address, leave the I/O address
unchanged, and repeat)
– INIRX (input from I/O, increment the memory address, leave the I/O address
unchanged, and repeat)
– OTDRX (output to I/O, decrement the memory address, leave the I/O address
unchanged, and repeat)
– OTIRX (output to I/O, increment the memory address, leave the I/O address
unchanged, and repeat)
• Four other block transfer instructions are modified to improve performance relative to
the eZ80190 device. These modified instructions are:
– IND2R (input from I/O, decrement the memory address, decrement the I/O
address, and repeat)
PS013012-1004
PRELIMINARY
eZ80® CPU Core