EZ80L92MCU Datasheet, PDF (90/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
75
Bit
Position
[1:0]
WDT_PERIOD
Value
00
01
10
11
Description
WDT time-out period is 2²⁷ clock cycles.
WDT time-out period is 2²⁵ clock cycles.
WDT time-out period is 2²² clock cycles.
WDT time-out period is 2¹⁸ clock cycles.
Note: *RST_FLAG is only cleared by a non-WDT RESET.
Watch-Dog Timer Reset Register
The Watch-Dog Timer Reset register, detailed in Table 28, is an 8-bit Write-Only register.
The Watch-Dog Timer is reset when an A5h value followed by 5Ah is written to this regis-
ter. Any amount of time can occur between the writing of the A5h value and the 5Ah value,
so long as the WDT time-out does not occur prior to completion.
Table 28. Watch-Dog Timer Reset Register (WDT_RR = 0094h)
Bit
7
6
5
4
3
2
1
0
Reset
X
X
X
X
X
X
X
X
CPU Access
W
W
W
W
W
W
W
W
Note: X = Undefined; W = Write only.
Bit
Position
[7:0]
WDT_RR
Value Description
A5h The first Write value required to reset the WDT prior to a time-
out.
5Ah The second Write value required to reset the WDT prior to a
time-out. If an A5h, 5Ah sequence is written to WDT_RR, the
WDT timer is reset to its initial count value, and counting
resumes.
PS013012-1004
PRELIMINARY
Watch-Dog Timer