EZ80L92MCU Datasheet, PDF (196/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
181
Bit
Position
4
ADL
3
MADL
2
IEF1
[1:0]
Reserved
Value Description
0
The CPU is operating in Z80 MEMORY mode.
(ADL bit = 0).
1
The CPU is operating in ADL MEMORY mode.
(ADL bit = 1).
0
The CPU’s Mixed-Memory mode (MADL) bit is reset to 0.
1
The CPU’s Mixed-Memory mode (MADL) bit is set to 1.
0
The CPU’s Interrupt Enable Flag 1 is reset to 0. Maskable
interrupts are disabled.
1
The CPU’s Interrupt Enable Flag 1 is set to 1. Maskable
interrupts are enabled.
00 Reserved.
ZDI Read Registers—Low, High, and Upper
The ZDI register Read-Only address space offers Low, High, and Upper functions, which
contain the value read by a Read operation from the ZDI Read/Write Control register
(ZDI_RW_CTL). This data is valid only while in ZDI BREAK mode and only if the
instruction is read by a request from the ZDI Read/Write Control register. See Table 104.
Table 104. ZDI Read Registers—Low, High and Upper (ZDI_RD_L = 10h, ZDI_RD_H
= 11h, and ZDI_RD_U = 12h in the ZDI Register Read-Only Address Space)
Bit
Reset
CPU Access
Note: R = Read-only.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Bit
Position
[7:0]
ZDI_RD_L,
ZDI_RD_H,
or
ZDI_RD_U
Value Description
00h–
FFh
Values read from the memory location as requested by
the ZDI Read Control register during a ZDI Read
operation. The 24-bit value is supplied by {ZDI_RD_U,
ZDI_RD_H, ZDI_RD_L}.
PS013012-1004
PRELIMINARY
ZiLOG Debug Interface