EZ80L92MCU Datasheet, PDF (126/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
111
These registers share the same address space as the UARTx_RBR and UARTx_BRG_L
registers. See Table 54.
Table 54. UART Transmit Holding Registers (UART0_THR = 00C0h, UART1_THR =
00D0h)
Bit
Reset
CPU Access
Note: W = Write only.
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
W
W
W
W
W
W
W
W
Bit
Position
[7:0]
TxD
Value
00h–
FFh
Description
Transmit data byte.
UART Receive Buffer Registers
The bits in this register reflect the data received. If less than eight bits are programmed for
receive, the lower bits of the byte reflect the bits received whereas upper unused bits are 0.
The receive FIFO is mapped at this address. If the FIFO is disabled, this buffer is only one
byte deep.
These registers share the same address space as the UARTx_THR and UARTx_BRG_L
registers. See Table 55.
Table 55. UART Receive Buffer Registers (UART0_RBR = 00C0h, UART1_RBR =
00 D0h)
Bit
Reset
CPU Access
Note: R = Read only.
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
R
R
R
R
R
R
R
R
Bit
Position
[7:0]
RxD
Value
00h–
FFh
Description
Receive data byte.
PS013012-1004
P R E L I M I N A R Y Universal Asynchronous Receiver/Transmitter