EZ80L92MCU Datasheet, PDF (168/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
153
mode) and then transmit the START condition. The STP bit is cleared automatically. Writ-
ing a 0 to this bit produces no effect.
The I²C Interrupt Flag (IFLG) is set to 1 automatically when any of 30 of the possible 31
I²C states is entered. The only state that does not set the IFLG bit is state F8h. If IFLG is
set to 1 and the IEN bit is also set, an interrupt is generated. When IFLG is set by the I²C,
the Low period of the I²C bus clock line is stretched and the data transfer is suspended.
When a 0 is written to IFLG, the interrupt is cleared and the I²C clock line is released.
When the I²C Acknowledge bit (AAK) is set to 1, an Acknowledge is sent during the
acknowledge clock pulse on the I²C bus if:
• Either the whole of a 7-bit slave address or the first or second byte of a 10-bit slave ad-
dress is received
• The general call address is received and the General Call Enable bit in I2C_SAR is set
to 1
• A data byte is received while in MASTER or SLAVE modes
When AAK is cleared to 0, a NACK is sent when a data byte is received in MASTER or
SLAVE mode. If AAK is cleared to 0 in the Slave Transmitter mode, the byte in the
I2C_DR register is assumed to be the final byte. After this byte is transmitted, the I²C
block enter states C8h, then returns to the idle state. The I²C module does not respond to
its slave address unless AAK is set. See Table 84.
PS013012-1004
PRELIMINARY
I²C Serial I/O Interface