EZ80L92MCU Datasheet, PDF (199/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
184
On-Chip Instrumentation
Introduction to On-Chip Instrumentation
On-Chip Instrumentation¹ (OCI™) for the ZiLOG eZ80^® CPU core enables powerful
debugging features. The OCI provides run control, memory and register visibility, com-
plex breakpoints, and trace history features.
The OCI employs all of the functions of the ZiLOG Debug Interface (ZDI) as described in
the ZDI section. It also adds the following debug features:
• Control via a 4-pin JTAG port that conforms to IEEE Standard 1149.1 (Test Access
Port and Boundary-Scan Architecture)²
• Complex break-point trigger functions
• Break-point enhancements, such as the ability to:
– Define two break-point addresses that form a range
– Break on masked data values
– Start or stop trace
– Assert a trigger output signal
• Trace history buffer
• Software break-point instruction
There are four sections to the OCI:
1. JTAG interface
2. ZDI debug control
3. Trace buffer memory
4. Complex triggers
OCI Activation
OCI features clock initialization circuitry so that external debug hardware can be detected
during power up. The external debugger must drive the OCI clock pin (TCK) Low at least
two system clock cycles prior to the end of the RESET to activate the OCI block. If TCK
is High at the end of the RESET, the OCI block shuts down so that it does not draw power
in normal product operation. When the OCI is shut down, ZDI is enabled directly and can
be accessed through the clock (TCK) and data (TDI) pins. See the ZiLOG Debug Interface
section on page 159 for more information about ZDI.
1. On-Chip Instrumentation and OCI are trademarks of First Silicon Solutions, Inc.
2. The eZ80L92 MCU does not contain the boundary scan register required for 1149.1 compliance.
PS013012-1004
PRELIMINARY
On-Chip Instrumentation