EZ80L92MCU Datasheet, PDF (187/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
172
ZDI Master Control Register
The ZDI Master Control register provides control of the eZ80L92. It is capable of forcing
a RESET and waking up the eZ80L92 from the low-power modes (HALT or SLEEP). See
Table 94.
Table 94. ZDI Master Control Register (ZDI_MASTER_CTL = 11h in ZDI Register
Write Address Spaces)
Bit
Reset
CPU Access
Note: W = Write-only.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Bit
Position
7
ZDI_RESET
[6:0]
Value Description
0
No action.
1
Initiate a RESET of the eZ80L92. This bit is
automatically cleared at the end of the RESET event.
0000000 Reserved.
PS013012-1004
PRELIMINARY
ZiLOG Debug Interface