EZ80L92MCU Datasheet, PDF (122/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
107
• Incorrect framing; that is, the stop bit is not detected by receiver at the end of the byte
• Receiver over run condition
• A BREAK condition being detected on the receive data input
An interrupt due to one of the above conditions is cleared when the UARTx_LSR register
is read. In FIFO mode, a line status interrupt is generated only after the received byte with
an error reaches the top of the FIFO and is ready to be read.
A line status interrupt is activated (provided this interrupt is enabled) as long as the Read
pointer of the receiver FIFO points to the location of the FIFO that contains a byte with the
error. The interrupt is immediately cleared when the UARTx_LSR register is read. The
ERR bit of the UARTx_LSR register is active as long as an erroneous byte is present in
the receiver FIFO.
UART Modem Status Interrupt
The modem status interrupt is generated if there is any change in state of the modem status
inputs to the UART. This interrupt is cleared when the processor reads the UARTx_MSR
register.
UART Recommended Usage
The following is the standard sequence of events that occur in the eZ80L92 using the
UART. A description of each follows.
1. Module reset.
2. Control transfers to configure UART operation.
3. Data transfers.
Module Reset. Upon reset, all internal registers are set to their default values. All com-
mand status registers are programmed with their default values, and the FIFOs are flushed.
Control Transfers. Based on the requirements of the application, the data transfer baud
rate is determined and the BRG is configured to generate a 16X clock frequency. Inter-
rupts are disabled and the communication control parameters are programmed in the
UARTx_LCTL register. The FIFO configuration is determined and the receive trigger lev-
els are set in the UARTx_FCTL register. The status registers, UARTx_LSR and
UARTx_MSR, are read, and ensure that none of the interrupt sources are active. The inter-
rupts are enabled (except for the transmit interrupt) and the application is ready to use the
module for transmission/reception.
Data Transfers—Transmit. To transmit data, the application enables the transmit inter-
rupt. An interrupt is immediately expected in response. The application reads the
PS013012-1004
P R E L I M I N A R Y Universal Asynchronous Receiver/Transmitter