EZ80L92MCU Datasheet, PDF (132/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
117
UART Modem Control Registers
This register is used to control and check the modem status. See Table 62.
Table 62. UART Modem Control Registers (UART0_MCTL = 00C4h, UART1_MCTL =
00D4h)
Bit
7
6
Reset
0
0
CPU Access
R
R
Note: R = Read only.; R/W = Read/Write.
5
4
3
2
1
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W
Bit
Position
[7:5]
4
LOOP
3
OUT2
2
OUT1
1
RTS
0
DTR
Value
000b
0
1
0–1
0–1
0–1
0–1
Description
Reserved.
LOOP BACK mode is not enabled.
LOOP BACK mode is enabled.
The UART operates in internal LOOP BACK mode. The
transmit data output port is disconnected from the internal
transmit data output and set to 1. The receive data input port
is disconnected and internal receive data is connected to
internal transmit data. The modem status input ports are
disconnected and the four bits of the modem control register
are connected as modem status inputs. The two modem
control output ports (OUT1&2) are set to their inactive state
No function in normal operation.
In LOOP BACK mode, this bit is connected to the DCD bit in
the UART Status Register.
No function in normal operation.
In LOOP BACK mode, this bit is connected to the RI bit in the
UART Status Register.
Request to Send.
In normal operation, the RTS output port is the inverse of this
bit. In LOOP BACK mode, this bit is connected to the CTS bit
in the UART Status Register.
Data Terminal Ready.
In normal operation, the DTR output port is the inverse of this
bit. In LOOP BACK mode, this bit is connected to the DSR bit
in the UART Status Register.
PS013012-1004
P R E L I M I N A R Y Universal Asynchronous Receiver/Transmitter