EZ80L92MCU Datasheet, PDF (164/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
149
is transmitted, the IFLG is set and the I2C_SR register contains C8h and the I²C returns to
the idle state. The AAK bit must be set to 1 before reentering SLAVE mode.
If no acknowledge is received after transmitting a byte, the IFLG is set and the I2C_SR
register contains C0h. The I²C then returns to the idle state.
If a STOP condition is detected after an acknowledge bit, the I²C returns to the idle state.
Slave Receive
In SLAVE RECEIVE mode, a number of data bytes are received from a master transmit-
ter.
The I²C enters SLAVE RECEIVE mode when it receives its own slave address and a
Write bit (lsb = 0) after a START condition. The I²C transmits an acknowledge bit and sets
the IFLG bit in the I2C_CTL register and the I2C_SR register contains the status code
60h. The I²C also enters SLAVE RECEIVE mode when it receives the general call
address 00h (if the GCE bit in the I2C_SAR register is set). The status code is then 70h.
Note: When the I²C contains a 10-bit slave address (signified by F0h–F7h in the
I2C_SAR register), it transmits an acknowledge after the first address byte is
received but no interrupt is generated. IFLG is not set and the status does not
change. The I²C generates an interrupt only after the second address byte is
received. The I²C sets the IFLG bit and loads the status code as described above.
I²C goes from MASTER mode to SLAVE RECEIVE mode when arbitration is lost during
the transmission of an address, and the slave address and Write bit (or the general call
address if the CGE bit in the I2C_SAR register is set to 1) are received. The status code in
the I2C_SR register is 68h if the slave address is received or 78h if the general call
address is received. The IFLG bit must be cleared to 0 to allow data transfer to continue.
If the AAK bit in the I2C_CTL register is set to 1 then an acknowledge bit (Low level on
SDA) is transmitted and the IFLG bit is set after each byte is received. The I2C_SR regis-
ter contains the status code 80h or 90h if SLAVE RECEIVE mode is entered with the
general call address. The received data byte can be read from the I2C_DR register and the
IFLG bit must be cleared to allow the transfer to continue. If a STOP condition or a
repeated START condition is detected after the acknowledge bit, the IFLG bit is set and
the I2C_SR register contains status code A0h.
If the AAK bit is cleared to 0 during a transfer, the I²C transmits a not-acknowledge bit
(High level on SDA) after the next byte is received, and set the IFLG bit. The I2C_SR reg-
ister contains the status code 88h or 98h if SLAVE RECEIVE mode is entered with the
general call address. The I²C returns to the idle state when the IFLG bit is cleared to 0.
PS013012-1004
PRELIMINARY
I²C Serial I/O Interface