EZ80L92MCU Datasheet, PDF (71/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
56
eZ80 Bus Mode
Signals (Pins)
INSTRD
RD
WR
WAIT
MREQ
IORQ
ADDR[23:0]
DATA[7:0]
Bus Mode
Controller
ADDR[7:0]
Multiplexed
Bus
Controller
Intel Bus
Signal Equvalents
ALE
RD
WR
READY
MREQ
IORQ
ADDR[23:0]
DATA[7:0]
Figure 9. Intel™ Bus Mode Signal and Pin Mapping
Intel Bus Mode (Separate Address and Data Buses)
During Read operations with separate address and data buses, the Intel Bus Mode employs
4 states (T1, T2, T3, and T4) as described in Table 16.
Table 16. Intel™ Bus Mode Read States (Separate Address and Data Buses)
STATE T1
STATE T2
The Read cycle begins in State T1. The CPU drives the address onto the
address bus and the associated Chip Select signal is asserted. The CPU
drives the ALE signal High at the beginning of T1. During the middle of T1,
the CPU drives ALE Low to facilitate the latching of the address.
During State T2, the CPU asserts the RD signal. Depending on the
instruction, either the MREQ or IORQ signal is asserted.
PS013012-1004
PRELIMINARY
Chip Selects and Wait States