EZ80L92MCU Datasheet, PDF (144/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
129
Serial Clock
The Serial Clock (SCK) is used to synchronize data movement both in and out of the
device through its MOSI and MISO pins. The master and slave are each capable of
exchanging a byte of data during a sequence of eight clock cycles. Because SCK is gener-
ated by the master, the SCK pin becomes an input on a slave device. The SPI contains an
internal divide-by-two clock divider. In MASTER mode, the SPI serial clock is one-half
the frequency of the clock signal created by the SPI’s Baud Rate Generator.
As demonstrated in Figure 29 and Table 68, four possible timing relations may be chosen
by using control bits CPOL and CPHA in the SPI Control register. See the SPI Control
Register (SPI_CTL) on page 134. Both the master and slave must operate with the identi-
cal timing, Clock Polarity (CPOL), and Clock Polarity (CPHA). The master device always
places data on the MOSI line a half-cycle before the clock edge (SCK signal), in order for
the slave device to latch the data.
Number of Cycles on the SCK Signal
1
2
3
4
5
6
7
8
SCK (CPOL bit = 0)
SCK (CPOL bit = 1)
Sample Input
(CPHA bit = 0) Data Out
MSB
6
5
4
3
2
1
LSB
Sample Input
(CPHA bit = 1) Data Out
Enable (To Slave)
MSB 6
5
4
3
2
1 LSB
Figure 29. SPI Timing
Table 68. SPI Clock Phase and Clock Polarity Operation
CPHA
0
0
CPOL
0
1
SCK
Transmit
Edge
Falling
Rising
SCK
Receive
Edge
Rising
Falling
SCK
Idle
State
Low
High
SS High
Between
Characters?
Yes
Yes
PS013012-1004
PRELIMINARY
Serial Peripheral Interface