EZ80L92MCU Datasheet, PDF (166/241 Pages) Zilog, Inc. – eZ80Acclaim Flash Microcontrollers

eZ80L92 MCU
Product Specification
151
Table 81. I²C Slave Address Register (I2C_SAR = 00C8h)
Bit
Reset
CPU Access
Note: R/W = Read/Write.
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Bit
Position
[7:1]
SLA
0
GCE
Value Description
00h–
7Fh
0
1
7-bit slave address or upper 2 bits,I2C_SAR[2:1], of address
when operating in 10-bit mode.
I²C not enabled to recognize the General Call Address.
I²C enabled to recognize the General Call Address.
I²C Extended Slave Address Register
The I2C_XSAR register is used in conjunction with the I2C_SAR register to provide 10-
bit addressing of the I²C when in SLAVE mode. The I2C_SAR value forms the lower 8
bits of the 10-bit slave address. The full 10-bit address is supplied by {I2C_SAR[2:1],
I2C_XSAR[7:0]}.
When the register receives an address starting with F7h to F0h (I2C_SAR[7:3] = 11110b),
the I²C recognizes that a 10-bit slave addressing mode is being selected. The I²C sends an
ACK after receiving the I2C_XSAR byte (the device does not generate an interrupt at this
point). After the next byte of the address (I2C_XSAR) is received, the I²C generates an
interrupt and goes into SLAVE mode. Then I2C_SAR[2:1] are used as the upper 2 bits for
the 10-bit extended address. The full 10-bit address is supplied by {I2C_SAR[2:1],
I2C_XSAR[7:0]}. See Table 82.
Table 82. I²C Extended Slave Address Register (I2C_XSAR = 00C9h)
Bit
Reset
CPU Access
Note: R/W = Read/Write.
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Bit
Position
[7:0]
SLAX
Value Description
00h– Least significant 8 bits of the 10-bit extended slave address.
FFh
PS013012-1004
PRELIMINARY
I²C Serial I/O Interface