MC68HC08AZ60 Datasheet, PDF (99/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
System Integration Module (SIM)
Low-Power Modes
break status register (SBSR). If the COP disable bit, COPD, in the
configuration register is logic 0, then the computer operating properly
module (COP) is enabled and remains active in wait mode.
IAB
WAIT ADDR
WAIT ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction.
Figure 12. Wait Mode Entry Timing
IAB
$6E0B
$6E0C
$00FF
$00FE
$00FD
$00FC
IDB $A6 $A6
$A6
$01
$0B
$6E
EXITSTOPWAIT
NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt OR break interrupt
Figure 13. Wait Recovery from Interrupt or Break
IAB
$6E0B
32
Cycles
IDB $A6 $A6
$A6
RST
CGMXCLK
32
Cycles
RSTVCTH RSTVCTL
Figure 14. Wait Recovery from Internal Reset
17-sim
MOTOROLA
MC68HC08AZ60 — Rev 1.0
System Integration Module (SIM)
99
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