MC68HC08AZ60 Datasheet, PDF (276/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Modulo Timer (TIM)
PS[2:0] — Prescaler Select Bits
These read/write bits select one of the seven prescaler outputs as the
input to the TIM counter as Table 2 shows. Reset clears the PS[2:0]
bits.
PS[2:0]
000
001
010
011
100
101
110
111
Table 2. Prescaler Selection
TIM Clock Source
Internal Bus Clock ÷1
Internal Bus Clock ÷ 2
Internal Bus Clock ÷ 4
Internal Bus Clock ÷ 8
Internal Bus Clock ÷ 16
Internal Bus Clock ÷ 32
Internal Bus Clock ÷ 64
Internal Bus Clock ÷ 64
TIM Counter
Registers
The two read-only TIM counter registers contain the high and low bytes
of the value in the TIM counter. Reading the high byte (TCNTH) latches
the contents of the low byte (TCNTL) into a buffer. Subsequent reads of
TCNTH do not affect the latched TCNTL value until TCNTL is read.
Reset clears the TIM counter registers. Setting the TIM reset bit (TRST)
also clears the TIM counter registers.
NOTE:
If you read TCNTH during a break interrupt, be sure to unlatch TCNTL
by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL
retains the value latched during the break.
Address: $004C
Bit 7
6
5
4
3
2
Read: Bit 15
14
13
12
11
10
Write:
Reset: 0
0
0
0
0
0
1
Bit 0
9
Bit 8
0
0
Figure 4. TIM Counter Registers (TCNTH–TCNTL)
MC68HC08AZ60 — Rev 1.0
276
Modulo Timer (TIM)
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