MC68HC08AZ60 Datasheet, PDF (89/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
System Integration Module (SIM)
Reset and System Initialization
nor the LVI was the source of the reset. See Table 3 for details. Figure
4 shows the relative timing.
Table 3. PIN Bit Set Timing
Reset Type
POR/LVI
All others
Number of Cycles Required to Set PIN
4163 (4096 + 64 + 3)
67 (64 + 3)
CGMOUT
RST
IAB
PC
VECT H VECT L
Figure 4. External Reset Timing
Active Resets from
Internal Sources
All internal reset sources actively pull the RST pin low for 32 CGMXCLK
cycles to allow resetting of external peripherals. The internal reset signal
IRST continues to be asserted for an additional 32 cycles (see Figure
5). An internal reset can be caused by an illegal address, illegal opcode,
COP timeout, LVI, or POR (see Figure 6). Note that for LVI or POR
resets, the SIM cycles through 4096 CGMXCLK cycles during which the
SIM forces the RST pin low. The internal reset signal then follows the
sequence from the falling edge of RST shown in Figure 5.
The COP reset is asynchronous to the bus clock.
The active reset feature allows the part to issue a reset to peripherals
and other chips within a system built around the MCU.
7-sim
MOTOROLA
MC68HC08AZ60 — Rev 1.0
System Integration Module (SIM)
89
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