MC68HC08AZ60 Datasheet, PDF (330/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
MSCAN Controller (MSCAN08)
Addr
Register Name
$05b0
IDENTIFIER REGISTER 0
$05b1
IDENTIFIER REGISTER 1
$05b2
IDENTIFIER REGISTER 2
$05b3
IDENTIFIER REGISTER 3
$05b4
DATA SEGMENT REGISTER 0
$05b5
DATA SEGMENT REGISTER 1
$05b6
DATA SEGMENT REGISTER 2
$05b7
DATA SEGMENT REGISTER 3
$05b8
DATA SEGMENT REGISTER 4
$05b9
DATA SEGMENT REGISTER 5
$05bA
DATA SEGMENT REGISTER 6
$05bB
DATA SEGMENT REGISTER 7
$05bC
DATA LENGTH REGISTER
$05bD
TRANSMIT BUFFER PRIORITY
REGISTER⁽¹⁾
$05bE
UNUSED
$05bF
UNUSED
1. Not applicable for receive buffers
Figure 10. Message Buffer Organization
Message Buffer
Outline
Figure 11 shows the common 13-byte data structure of receive and
transmit buffers for extended identifiers. The mapping of standard
identifiers into the IDR registers is shown in Figure 12. All bits of the
13-byte data structure are undefined out of reset.
NOTE: The foreground receive buffer can be read anytime but cannot be
written. The transmit buffers can be read or written anytime.
Identifier Registers
The identifiers consist of either 11 bits (ID10–ID0) for the standard, or 29
bits (ID28–ID0) for the extended format. ID10/28 is the most significant
bit and is transmitted first on the bus during the arbitration procedure.
The priority of an identifier is defined to be highest for the smallest binary
number.
MC68HC08AZ60 — Rev 1.0
330
MSCAN Controller (MSCAN08)
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