MC68HC08AZ60 Datasheet, PDF (280/452 Pages) Motorola, Inc – Advance Information

I/O Ports
Freescale Semiconductor, Inc.
Introduction
Fifty bidirectional input/output (I/O) form seven parallel ports. All I/O pins
are programmable as inputs or outputs.
NOTE:
Connect any unused I/O pins to an appropriate logic level, either V_DD or
V_SS. Although the I/O ports do not require termination for proper
operation, termination reduces excess current consumption and the
possibility of electrostatic damage.
Addr.
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
Register Name
Bit 7
6
5
4
3
2
1 Bit 0
Port A Data Register (PTA) PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0
Port B Data Register (PTB) PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
Port C Data Register (PTC) 0
0 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0
Port D Data Register (PTD) PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0
Data Direction Register A (DDRA) DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Data Direction Register B (DDRB) DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
Data Direction Register C (DDRC) MCLKEN 0 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
Data Direction Register D (DDRD) DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0
Port E Data Register (PTE) PTE7 PTE6 PTE5 PTE4 PTE3 PTE2 PTE1 PTE0
Port F Data Register (PTF) 0
PTF6 PTF5 PTF4 PTF3 PTF2 PTF1 PTF0
Port G Data Register (PTG) 0
0
0
0
0 PTG2 PTG1 PTG0
Port H Data Register (PTH) 0
0
0
0
0
0 PTH1 PTH0
Data Direction Register E (DDRE) DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0
Data Direction Register F (DDRF) 0 DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0
Data Direction Register G (DDRG) 0
0
0
0
0 DDRG2 DDRG1 DDRG0
Data Direction Register H (DDRH) 0
0
0
0
0
0 DDRH1‘ DDRH0
Figure 1. CAN Protocol I/O Port Register Summary
MC68HC08AZ60 — Rev 1.0
280
I/O Ports
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Go to: www.freescale.com
2-ioports
MOTOROLA