MC68HC08AZ60 Datasheet, PDF (429/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Appendix B: HC08AZ48 Memory Map
I/O Section
Addr.
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
Register Name
Bit 7
6
5
Read:
Port A Data Register (PTA)
PTA7
Write:
PTA6
PTA5
Read:
Port B Data Register (PTB)
PTB7
Write:
PTB6
PTB5
Read: 0
Port C Data Register (PTC)
Write:
0
PTC5
Read:
Port D Data Register (PTD)
PTD7
Write:
PTD6
PTD5
Data Direction Register A ^Read:
(DDRA) _Write:
DDRA7
DDRA6
DDRA5
Data Direction Register B ^Read:
(DDRB) _Write:
DDRB7
DDRB6
DDRB5
Data Direction Register C
(DDRC)
Read:
Write:
MCLKEN
0
DDRC5
Data Direction Register D ^Read:
(DDRD) _Write:
DDRD7
DDRD6
DDRD5
Read:
Port E Data Register (PTE)
PTE7
Write:
PTE6
PTE5
Read: 0
Port F Data Register (PTF)
Write:
PTF6 PTF5
Read: 0
0
0
Port G Data Register (PTG)
Write:
Read: 0
0
0
Port H Data Register (PTH)
Write:
Data Direction Register E ^Read:
(DDRE) _Write:
DDRE7
DDRE6
DDRE5
Data Direction Register F ^{Read: 0}
(DDRF) _Write:
DDRF6 DDRF5
Data Direction Register G ^{Read: 0}
0
0
(DDRG) _Write:
Data Direction Register H ^{Read: 0}
0
0
(DDRH) _Write:
Read:
SPI Control Register (SPCR)
SPRIE
Write:
R SPMSTR
4
PTA4
PTB4
PTC4
PTD4
DDRA4
DDRB4
DDRC4
DDRD4
PTE4
PTF4
0
0
DDRE4
DDRF4
0
0
CPOL
3
PTA3
PTB3
PTC3
PTD3
DDRA3
DDRB3
DDRC3
DDRD3
PTE3
PTF3
0
0
DDRE3
DDRF3
0
0
CPHA
2
1
PTA2 PTA1
PTB2 PTB1
PTC2 PTC1
PTD2 PTD1
DDRA2 DDRA1
DDRB2 DDRB1
DDRC2 DDRC1
DDR2 DDRD1
PTE2 PTE1
PTF2 PTF1
PTG2 PTG1
0
PTH1
DDRE2 DDRE1
DDRF2 DDRF1
DDRG2 DDRG1
0
DDRH1
SPWOM SPE
Bit 0
PTA0
PTB0
PTC0
PTD0
DDRA0
DDRB0
DDRC0
DDRD0
PTE0
PTF0
PTG0
PTH0
DDRE0
DDRF0
DDRG0
DDRH0
SPTIE
5-mem48
MOTOROLA
= Unimplemented
R = Reserved
Figure 2. Control, Status, and Data Registers (Sheet 1 of 6)
MC68HC08AZ60 — Rev 1.0
Appendix B: HC08AZ48 Memory Map
429
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