MC68HC08AZ60 Datasheet, PDF (96/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
System Integration Module (SIM)
MODULE
INTERRUPT
I BIT
IAB
IDB
R/W
SP – 4 SP – 3 SP – 2 SP – 1
SP
PC
PC + 1
CCR
A
X
PC – 1 [7:0] PC–1[15:8] OPCODE OPERAND
Figure 10. Interrupt Recovery
Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing
of a hardware interrupt begins after completion of the current
instruction. When the current instruction is complete, the SIM checks
all pending hardware interrupts. If interrupts are not masked (I bit
clear in the condition code register), and if the corresponding interrupt
enable bit is set, the SIM proceeds with interrupt processing;
otherwise, the next instruction is fetched and executed.
If more than one interrupt is pending at the end of an instruction
execution, the highest priority interrupt is serviced first. Figure 11
demonstrates what happens when two interrupts are pending. If an
interrupt is pending upon exit from the original interrupt service
routine, the pending interrupt is serviced before the LDA instruction is
executed.
The LDA opcode is prefetched by both the INT1 and INT2 RTI
instructions. However, in the case of the INT1 RTI prefetch, this is a
redundant operation.
NOTE:
To maintain compatibility with the M68HC05, M6805 and M146805
Families the H register is not pushed on the stack during interrupt entry.
If the interrupt service routine modifies the H register or uses the indexed
addressing mode, software should save the H register and then restore
it prior to exiting the routine.
MC68HC08AZ60 — Rev 1.0
96
System Integration Module (SIM)
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