MC68HC08AZ60 Datasheet, PDF (239/452 Pages) Motorola, Inc – Advance Information

29-spi
MOTOROLA
Freescale Semiconductor, Inc.
Serial Peripheral Interface Module (SPI)
I/O Registers
Address: $0011
Bit 7
6
5
4
3
2
1
Read: SPRF
Write: R
ERRIE
OVRF
R
MODF
R
SPTE
MODFEN SPR1
R
Reset: 0
0
0
0
1
0
0
R = Reserved
Figure 12. SPI Status and Control Register (SPSCR)
Bit 0
SPR0
0
SPRF — SPI Receiver Full Bit
This clearable, read-only flag is set each time a byte transfers from
the shift register to the receive data register. SPRF generates a CPU
interrupt request if the SPRIE bit in the SPI control register is set also.
During an SPRF CPU interrupt, the CPU clears SPRF by reading the
SPI status and control register with SPRF set and then reading the
SPI data register. Any read of the SPI data register clears the SPRF
bit.
Reset clears the SPRF bit.
1 = Receive data register full
0 = Receive data register not full
ERRIE — Error Interrupt Enable Bit
This read-only bit enables the MODF and OVRF flags to generate
CPU interrupt requests. Reset clears the ERRIE bit.
1 = MODF and OVRF can generate CPU interrupt requests
0 = MODF and OVRF cannot generate CPU interrupt requests
OVRF — Overflow Bit
This clearable, read-only flag is set if software does not read the byte
in the receive data register before the next byte enters the shift
register. In an overflow condition, the byte already in the receive data
register is unaffected, and the byte that shifted in last is lost. Clear the
OVRF bit by reading the SPI status and control register with OVRF set
and then reading the SPI data register. Reset clears the OVRF flag.
1 = Overflow
0 = No overflow
MC68HC08AZ60 — Rev 1.0
Serial Peripheral Interface Module (SPI)
239
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