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MC68HC08AZ60 Datasheet, PDF (258/452 Pages) Motorola, Inc – Advance Information | |||
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Freescale Semiconductor, Inc.
Timer Interface Module B (TIMB)
I/O Registers
These I/O registers control and monitor TIMB operation:
⢠TIMB status and control register (TBSC)
⢠TIMB control registers (TBCNTHâTBCNTL)
⢠TIMB counter modulo registers (TBMODHâTBMODL)
⢠TIMB channel status and control registers (TBSC0 and TBSC1)
⢠TIMB channel registers (TBCH0HâTBCH0L, TBCH1HâTBCH1L)
TIMB Status and
Control Register
The TIMB status and control register:
⢠Enables TIMB overflow interrupts
⢠Flags TIMB overflows
⢠Stops the TIMB counter
⢠Resets the TIMB counter
⢠Prescales the TIMB counter clock
Address: $0040
Bit 7
6
5
4
3
2
1
Bit 0
Read: TOF
0
0
TOIE TSTOP
Write: 0
TRST
R
PS2
PS1
PS0
Reset: 0
0
1
0
0
0
0
0
R = Reserved
Figure 4. TIMB Status and Control Register (TBSC)
TOF â TIMB Overflow Flag Bit
This read/write flag is set when the TIMB counter resets to $0000 after
reaching the modulo value programmed in the TIMB counter modulo
registers. Clear TOF by reading the TIMB status and control register
when TOF is set and then writing a logic 0 to TOF. If another TIMB
overflow occurs before the clearing sequence is complete, then
MC68HC08AZ60 â Rev 1.0
258
Timer Interface Module B (TIMB)
For More Information On This Product,
Go to: www.freescale.com
16-timb
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