MC68HC08AZ60 Datasheet, PDF (90/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
System Integration Module (SIM)
IRST
RST
CGMXCLK
IAB
RST PULLED LOW BY MCU
32 CYCLES
32 CYCLES
Figure 5. Internal Reset Timing
VECTOR HIGH
Power-On Reset
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
LVI
POR
INTERNAL RESET
Figure 6. Sources of Internal Reset
When power is first applied to the MCU, the power-on reset module
(POR) generates a pulse to indicate that power-on has occurred. The
external reset pin (RST) is held low while the SIM counter counts out
4096 CGMXCLK cycles. Another sixty-four CGMXCLK cycles later, the
CPU and memories are released from reset to allow the reset vector
sequence to occur.
At power-on, the following events occur:
• A POR pulse is generated.
• The internal reset signal is asserted.
• The SIM enables CGMOUT.
• Internal clocks to the CPU and modules are held inactive for 4096
CGMXCLK cycles to allow stabilization of the oscillator.
• The RST pin is driven low during the oscillator stabilization time.
• The POR bit of the SIM reset status register (SRSR) is set and all
other bits in the register are cleared.
MC68HC08AZ60 — Rev 1.0
90
System Integration Module (SIM)
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8-sim
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