MC68HC08AZ60 Datasheet, PDF (348/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
MSCAN Controller (MSCAN08)
MSCAN08
Transmitter Control
Register
Address: $0507
Bit 7
6
5
4
3
2
1
Read: 0
0
ABTRQ2 ABTRQ1 ABTRQ0
Write:
TXEIE2 TXEIE1
Reset: 0
0
0
0
0
0
0
= Unimplemented
Figure 22. Transmitter Control Register (CTCR)
Bit 0
TXEIE0
0
ABTRQ2–ABTRQ0 — Abort Request
The CPU sets an ABTRQx bit to request that an already scheduled
message buffer (TXE = 0) be aborted. The MSCAN08 will grant the
request if the message has not already started transmission, or if the
transmission is not successful (lost srbitration or error). When a
message is aborted the associated TXE and the abort acknowledge
flag (ABTAK) (see MSCAN08 Transmitter Flag Register on page
346) will be set and an TXE interrupt is generated if enabled. The
CPU cannot reset ABTRQx. ABTRQx is cleared implicitly whenever
the associated TXE flag is set.
1 = Abort request pending
0 = No abort request
NOTE: The software must not clear one or more of the TXE flags in CTFLG and
simultaneaously set the respective ABTRQ bit(s).
TXEIE2–TXEIE0 — Transmitter Empty Interrupt Enable
1 = A transmitter empty (transmit buffer available for transmission)
event results in a transmitter empty interrupt.
0 = No interrupt is generated from this event.
NOTE: The CTCR register is held in the reset state when the SFTRES bit in
CMCR0 is set.
MC68HC08AZ60 — Rev 1.0
348
MSCAN Controller (MSCAN08)
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