MC68HC08AZ60 Datasheet, PDF (160/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Low-Voltage Inhibit (LVI)
Introduction
This section describes the low-voltage inhibit module, which monitors
the voltage on the V_DD pin and can force a reset when the V_DD voltage
falls to the LVI trip voltage.
Features
Features of the LVI module include:
NOTE:
• Programmable LVI Reset
• Programmable Power Consumption
• Digital Filtering of V_DD Pin Level
If a low voltage interrupt (LVI) occurs during programming of EEPROM
memory, then adequate programming time may may not have been
allowed to ensure the integrity and retention of the data. It is the
responsibility of the user to ensure that in the event of an LVI any
addresses being programmed receive specification programming
conditions.
Functional Description
Figure 1 shows the structure of the LVI module. The LVI is enabled out
of reset. The LVI module contains a bandgap reference circuit and
comparator. The LVI power bit, LVIPWR, enables the LVI to monitor V_DD
voltage. The LVI reset bit, LVIRST, enables the LVI module to generate
a reset when V_DD falls below a voltage, LVI_TRIPF, and remains at or
below that level for nine or more consecutive CPU cycles.
Note that short V_DD spikes may not trip the LVI. It is the user’s
responsibility to ensure a clean V_DD signal within the specified
operating voltage range if normal microcontroller operation is to be
guaranteed.
MC68HC08AZ60 — Rev 1.0
160
Low-Voltage Inhibit (LVI)
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