MC68HC08AZ60 Datasheet, PDF (294/452 Pages) Motorola, Inc – Advance Information

I/O Ports
Freescale Semiconductor, Inc.
TxD — SCI Transmit Data Output
The PTE0/TxD pin is the transmit data output for the SCI module.
When the enable SCI bit, ENSCI, is clear, the SCI module is disabled,
and the PTE0/TxD pin is available for general-purpose I/O. (See SCI
Control Register 1 on page 194).
NOTE:
Data direction register E (DDRE) does not affect the data direction of
port E pins that are being used by the SCI module. However, the DDRE
bits always determine whether reading port E returns the states of the
latches or the states of the pins. (See Table 5).
Data Direction
Register E
Data direction register E determines whether each port E pin is an input
or an output. Writing a logic 1 to a DDRE bit enables the output buffer for
the corresponding port E pin; a logic 0 disables the output buffer.
Address: $000C
Bit 7
6
5
4
3
2
1
Read:
DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1
Write:
Reset: 0
0
0
0
0
0
0
Figure 15. Data Direction Register E (DDRE)
Bit 0
DDRE0
0
DDRE[7:0] — Data Direction Register E Bits
These read/write bits control port E data direction. Reset clears
DDRE[7:0], configuring all port E pins as inputs.
1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input
NOTE: Avoid glitches on port E pins by writing to the port E data register before
changing data direction register E bits from 0 to 1.
Figure 16 shows the port E I/O logic.
MC68HC08AZ60 — Rev 1.0
294
I/O Ports
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16-ioports
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