MC68HC08AZ60 Datasheet, PDF (88/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
System Integration Module (SIM)
Clocks in Stop
Mode and Wait
Mode
Upon exit from stop mode by an interrupt, break, or reset, the SIM allows
CGMXCLK to clock the SIM counter. The CPU and peripheral clocks do
not become active until after the stop delay timeout. This timeout is
selectable as 4096 or 32 CGMXCLK cycles. See Stop Mode on page
100.
In wait mode, the CPU clocks are inactive. Refer to the wait mode
subsection of each module to see if the module is active or inactive in
wait mode. Some modules can be programmed to be active in wait
mode.
Reset and System Initialization
The MCU has these reset sources:
• Power-on reset module (POR)
• External reset pin (RST)
• Computer operating properly module (COP)
• Low-voltage inhibit module (LVI)
• Illegal opcode
• Illegal address
All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in
monitor mode) and assert the internal reset signal (IRST). IRST causes
all registers to be returned to their default values and all modules to be
returned to their reset states.
An internal reset clears the SIM counter (see SIM Counter on page 93),
but an external reset does not. Each of the resets sets a corresponding
bit in the SIM reset status register (SRSR) (see SIM Registers on page
101).
External Pin Reset
Pulling the asynchronous RST pin low halts all processing. The PIN bit
of the SIM reset status register (SRSR) is set as long as RST is held low
for a minimum of 67 CGMXCLK cycles, assuming that neither the POR
MC68HC08AZ60 — Rev 1.0
88
System Integration Module (SIM)
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