MC68HC08AZ60 Datasheet, PDF (247/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Timer Interface Module B (TIMB)
Functional Description
Functional Description
Figure 1 shows the TIMB structure. The central component of the TIMB
is the 16-bit TIMB counter that can operate as a free-running counter or
a modulo up-counter. The TIMB counter provides the timing reference
for the input capture and output compare functions. The TIMB counter
modulo registers, TBMODH–TBMODL, control the modulo value of the
TIMB counter. Software can read the TIMB counter value at any time
without affecting the counting sequence.
The two TIMB channels are programmable independently as input
capture or output compare channels.
TIMB Counter
Prescaler
The TIMB clock source can be one of the seven prescaler outputs or the
TIMB clock pin, PTD4/TBLCK. The prescaler generates seven clock
rates from the internal bus clock. The prescaler select bits, PS[2:0], in
the TIMB status and control register select the TIMB clock source.
Input Capture
5-timb
MOTOROLA
An input capture function has three basic parts: edge select logic, an
input capture latch, and a 16-bit counter. Two 8-bit registers, which make
up the 16-bit input capture register, are used to latch the value of the
free-running counter after the corresponding input capture edge detector
senses a defined transition. The polarity of the active edge is
programmable. The level transition which triggers the counter transfer is
defined by the corresponding input edge bits (ELSxB and ELSxA in
TBSC0 through TBSC1 control registers with x referring to the active
channel number). When an active edge occurs on the pin of an input
capture channel, the TIMB latches the contents of the TIMB counter into
the TIMB channel registers, TCHxH–TCHxL. Input captures can
generate TIMB CPU interrupt requests. Software can determine that an
input capture event has occurred by enabling input capture interrupts or
by polling the status flag bit.
The result obtained by an input capture will be two more than the value
of the free-running counter on the rising edge of the internal bus clock
preceding the external transition. This delay is required for internal
synchronization.
MC68HC08AZ60 — Rev 1.0
Timer Interface Module B (TIMB)
247
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