MC68HC08AZ60 Datasheet, PDF (137/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Break Module
Functional Description
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Break Address Register High
(BRKH)
Write:
Bit 15
14
13
12
11
10
Reset: 0
0
0
0
0
0
9
Bit 8
0
0
Read:
Break Address Register Low
(BRKL)
Write:
Bit 7
6
5
4
3
2
1
Bit 0
Reset: 0
0
0
0
0
0
0
0
Read:
0
0
0
0
0
0
Break Status and Control Register
(BSCR)
Write:
BRKE
BRKA
Reset: 0
0
0
0
0
0
0
0
= Unimplemented R = Reserved
Figure 2. I/O Register Summary
Table 1. I/O Register Address Summary
Register
Address
BRKH
$FE0C
BRKL
$FE0D
BSCR
$FE0E
Flag Protection
During Break
Interrupts
The BCFE bit in the break flag control register (BFCR) enables software
to clear status bits during the break state.
CPU During Break
Interrupts
The CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC:$FFFD ($FEFC:$FEFD
in monitor mode)
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
3-brk
MOTOROLA
MC68HC08AZ60 — Rev 1.0
Break Module
137
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