MC68HC08AZ60 Datasheet, PDF (225/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Serial Peripheral Interface Module (SPI)
Error Conditions
BYTE 1
SPI RECEIVE
1
COMPLETE
SPRF
BYTE 2
5
BYTE 3
7
BYTE 4
11
OVRF
READ SPSCR
2
4
6
9
12
14
READ SPDR
3
8
10
13
1 BYTE 1 SETS SPRF BIT.
2 CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
3 CPU READS BYTE 1 IN SPDR,
CLEARING SPRF BIT.
4 CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
5 BYTE 2 SETS SPRF BIT.
6 CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
7 BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
8 CPU READS BYTE 2 IN SPDR,
CLEARING SPRF BIT.
9 CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
10 CPU READS BYTE 2 SPDR,
CLEARING OVRF BIT.
11 BYTE 4 SETS SPRF BIT.
12 CPU READS SPSCR.
13 CPU READS BYTE 4 IN SPDR,
CLEARING SPRF BIT.
14 CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
Figure 7. Clearing SPRF When OVRF Interrupt Is Not Enabled
Mode Fault Error
For the MODF flag (in SPSCR) to be set, the mode fault error enable bit
(MODFEN in SPSCR) must be set. Clearing the MODFEN bit does not
clear the MODF flag but does prevent MODF from being set again after
MODF is cleared.
MODF generates a receiver/error CPU interrupt request if the error
interrupt enable bit (ERRIE in SPSCR) is also set. The SPRF, MODF,
and OVRF interrupts share the same CPU interrupt vector. MODF and
OVRF can generate a receiver/error CPU interrupt request. (See Figure
8). It is not possible to enable only MODF or OVRF to generate a
receiver/error CPU interrupt request. However, leaving MODFEN low
prevents MODF from being set.
15-spi
MOTOROLA
MC68HC08AZ60 — Rev 1.0
Serial Peripheral Interface Module (SPI)
225
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