MC68HC08AZ60 Datasheet, PDF (157/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Computer Operating Properly Module (COP)
COP Control Register
COP Control Register
The COP control register is located at address $FFFF and overlaps the
reset vector. Writing any value to $FFFF clears the COP counter and
starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
Address: $FFFF
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Low Byte of Reset Vector
Write:
Clear COP Counter
Reset:
Unaffected by Reset
Figure 2. COP Control Register (COPCTL)
Interrupts
The COP does not generate CPU interrupt requests.
Monitor Mode
The COP is disabled in monitor mode when V_Hi is present on the IRQ
pin or on the RST pin.
5-cop
MOTOROLA
MC68HC08AZ60 — Rev 1.0
Computer Operating Properly Module (COP)
157
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