MC68HC08AZ60 Datasheet, PDF (297/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
I/O Ports
Port F
TBCH[1:0] — Timer B Channel I/O Bits
The PTF5/TBCH1–PTF4/TBCH0 pins are the TIMB input
capture/output compare pins. The edge/level select bits,
ELSxB:ELSxA, determine whether the PTF5/TBCH1–PTF4/TBCH0
pins are timer channel I/O pins or general-purpose I/O pins. (See TIM
Status and Control Register on page 274).
NOTE:
Data direction register F (DDRF) does not affect the data direction of port
F pins that are being used by the TIM. However, the DDRF bits always
determine whether reading port F returns the states of the latches or the
states of the pins. (See Table 6).
Data Direction
Register F
Data direction register F determines whether each port F pin is an input
or an output. Writing a logic 1 to a DDRF bit enables the output buffer for
the corresponding port F pin; a logic 0 disables the output buffer.
Address: $000D
Bit 7
6
5
4
3
2
1
Read: 0
Write: R
DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1
Reset: 0
0
0
0
0
0
0
R = Reserved
Figure 18. Data Direction Register F (DDRF)
Bit 0
DDRF0
0
DDRF[6:0] — Data Direction Register F Bits
These read/write bits control port F data direction. Reset clears
DDRF[6:0], configuring all port F pins as inputs.
1 = Corresponding port F pin configured as output
0 = Corresponding port F pin configured as input
NOTE: Avoid glitches on port F pins by writing to the port F data register before
changing data direction register F bits from 0 to 1.
Figure 19 shows the port F I/O logic.
19-ioports
MOTOROLA
MC68HC08AZ60 — Rev 1.0
I/O Ports
297
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