MC68HC08AZ60 Datasheet, PDF (235/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Serial Peripheral Interface Module (SPI)
I/O Signals
state of the MODFEN control bit. However, the MODFEN bit can still
prevent the state of the SS from creating a MODF error. (See SPI Status
and Control Register on page 238).
NOTE:
A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a
high-impedance state. The slave SPI ignores all incoming SPSCK
clocks, even if a transmission already has begun.
When an SPI is configured as a master, the SS input can be used in
conjunction with the MODF flag to prevent multiple masters from driving
MOSI and SPSCK. (See Mode Fault Error on page 225). For the state
of the SS pin to set the MODF flag, the MODFEN bit in the SPSCK
register must be set. If the MODFEN bit is low for an SPI master, the SS
pin can be used as a general-purpose I/O under the control of the data
direction register of the shared I/O port. With MODFEN high, it is an
input-only pin to the SPI regardless of the state of the data direction
register of the shared I/O port.
The CPU can always read the state of the SS pin by configuring the
appropriate pin as an input and reading the data register. (See Table 5).
Table 5. SPI Configuration
SPE SPMSTR MODFEN SPI Configuration
0
X
X
Not Enabled
1
0
X
Slave
1
1
0
Master without MODF
1
1
1
Master with MODF
X = don’t care
State of SS Logic
General-Purpose I/O;
SS Ignored by SPI
Input-Only to SPI
General-Purpose I/O;
SS Ignored by SPI
Input-Only to SPI
V_SS (Clock
Ground)
V_SS is the ground return for the serial clock pin, SPSCK, and the ground
for the port output buffers. To reduce the ground return path loop and
minimize radio frequency (RF) emissions, connect the ground pin of the
slave to the V_SS pin.
25-spi
MOTOROLA
MC68HC08AZ60 — Rev 1.0
Serial Peripheral Interface Module (SPI)
235
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