MC68HC08AZ60 Datasheet, PDF (290/452 Pages) Motorola, Inc – Advance Information

I/O Ports
Freescale Semiconductor, Inc.
DDRD bits always determine whether reading port D returns the states
of the latches or logic 0.
TACLK/TBCLK — Timer Clock Input Bit
The PTD6/TACLK pin is the external clock input for the TIMA. The
PTD4/TBLCK pin is the external clock input for the TIMB. The
prescaler select bits, PS[2:0], select PTD6/TACLK or PTD4/TBLCK
as the TIM clock input. (See TIMA Channel Status and Control
Registers on page 384 and TIMB Channel Status and Control
Registers on page 262). When not selected as the TIM clock,
PTD6/TACLK and PTD4/TBLCK are available for general-purpose I/O.
While TACLK/TBCLK are selected corresponding DDRD bits have no
effect.
Data Direction
Register D
Data direction register D determines whether each port D pin is an input
or an output. Writing a logic 1 to a DDRD bit enables the output buffer
for the corresponding port D pin; a logic 0 disables the output buffer.
Address: $0007
Bit 7
6
5
4
3
2
1
Read:
DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1
Write:
Reset: 0
0
0
0
0
0
0
Figure 12. Data Direction Register D (DDRD)
Bit 0
DDRD0
0
DDRD[7:0] — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears
DDRD[7:0], configuring all port D pins as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
NOTE: Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Figure 13 shows the port D I/O logic.
MC68HC08AZ60 — Rev 1.0
290
I/O Ports
For More Information On This Product,
Go to: www.freescale.com
12-ioports
MOTOROLA