MC68HC08AZ60 Datasheet, PDF (378/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Timer Interface Module A (TIMA-6)
TIMA During Break Interrupts
A break interrupt stops the TIMA counter and inhibits input captures.
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. (See SIM Break Flag Control
Register on page 103).
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a 2-step read/write clearing procedure. If software does
the first step on such a bit before the break, the bit cannot change during
the break state as long as BCFE is at logic 0. After the break, doing the
second step clears the status bit.
MC68HC08AZ60 — Rev 1.0
378
Timer Interface Module A (TIMA-6)
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