MC68HC08AZ60 Datasheet, PDF (186/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Serial Communications Interface Module (SCI)
START BIT
LSB
RxD
SAMPLES
RT
CLOCK
RT CLOCK
STATE
RT CLOCK
RESET
START BIT
START BIT
DATA
QUALIFICATION VERIFICATION SAMPLING
Figure 8. Receiver Data Sampling
To verify the start bit and to detect noise, data recovery logic takes
samples at RT3, RT5, and RT7. Table 5 summarizes the results of the
start bit verification samples.
Table 5. Start Bit Verification
RT3, RT5, and RT7 Samples
000
001
010
011
100
101
110
111
Start Bit Verification
Yes
Yes
Yes
No
Yes
No
No
No
Noise Flag
0
1
1
0
1
0
0
0
If start bit verification is not successful, the RT clock is reset and a new
search for a start bit begins.
MC68HC08AZ60 — Rev 1.0
186
Serial Communications Interface Module (SCI)
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