MC68HC08AZ60 Datasheet, PDF (101/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
System Integration Module (SIM)
SIM Registers
CGMXCLK
INT/BREAK
IAB
STOP RECOVERY PERIOD
STOP +1
STOP + 2 STOP + 2
SP
SP – 1
SP – 2
SP – 3
Figure 16. Stop Mode Recovery from Interrupt or Break
SIM Registers
The SIM has three memory mapped registers.
SIM Break Status
Register
The SIM break status register contains a flag to indicate that a break
caused an exit from stop or wait mode.
Address: $FE00
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SBSW
R
R
R
R
R
R
R
Write:
See Note
Reset:
0
R
= Reserved
NOTE: Writing a logic 0 clears SBSW
Figure 17. SIM Break Status Register (SBSR)
SBSW — SIM Break Stop/Wait
This status bit is useful in applications requiring a return to wait or stop
mode after exiting from a break interrupt. Clear SBSW by writing a
logic 0 to it. Reset clears SBSW.
1 = Stop mode or wait mode was exited by break interrupt
0 = Stop mode or wait mode was not exited by break interrupt
SBSW can be read within the break state SWI routine. The user can
modify the return address on the stack by subtracting one from it. The
19-sim
MOTOROLA
MC68HC08AZ60 — Rev 1.0
System Integration Module (SIM)
101
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