MC68HC08AZ60 Datasheet, PDF (423/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Appendix A: Future EEPROM Registers
EEDIV Non-volatile Registers
EEDIVSECD — EEPROM Divider Security Disable
This bit enables/disables the security feature of the EEDIV registers.
When EEDIV security feature is enabled, the state of the registers
EEDIVH and EEDIVL are locked (inclucding this EEDIVSECD bit).
Also the EEDIVHNVR and EEDIVLNVR non-volatile memory
registers are protected from being erased/programmed.
1 = EEDIV security feature disabled
0 = EEDIV security feature enabled
EEDIV10–EEDIV0 — EEPROM timebase prescalar.
These prescalar bits store the value of EEDIV which is used as the
divisor to derive a timebase of 35µs from the selected reference clock
source for the EEPROM related internal timer and circuits.
EEDIV0–10 are readable at any time. They are writable when EELAT
is not set and EEDIVSECD is not cleared.
EEDIV Non-volatile Registers
Address: $FE10
Bit 7
6
5
4
3
2
1
Bit 0
Read:
EEDIVSECD
Write:
EEDIV10 EEDIV9 EEDIV8
Reset: PV
PV
PV
PV
PV
PV
PV
PV
= Unimplemented
Figure 5. EEPROM-2 Divider High Non-volatile Register (EEDIVHNVR)
Address: $FE11
Bit 7
6
5
4
3
2
1
Bit 0
Read:
EEDIV7
Write:
EEDIV6
EEDIV5
EEDIV4
EEDIV3
EEDIV2
EEDIV1
EEDIV0
Reset: PV
PV
PV
PV
PV
PV
PV
PV
= Unimplemented
Figure 6. EEPROM-2 Divider Low Non-volatile Register (EEDIVLNVR)
3-appA
MOTOROLA
MC68HC08AZ60 — Rev 1.0
Appendix A: Future EEPROM Registers
423
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