MC68HC08AZ60 Datasheet, PDF (257/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Timer Interface Module B (TIMB)
I/O Signals
I/O Signals
Port D shares one of its pins with the TIMB. Port F shares two of its pins
with the TIMB. PTD4/TBLCK is an external clock input to the TIMB
prescaler. The two TIMB channel I/O pins are PTF4/TBCH0 and
PTF5/TBCH1.
TIMB Clock Pin
(PTD4/TBLCK)
PTD4/TBLCK is an external clock input that can be the clock source for
the TIMB counter instead of the prescaled internal bus clock. Select the
PTD4/TBLCK input by writing logic 1s to the three prescaler select bits,
PS[2:0]. (See TIMB Status and Control Register.) The minimum TCLK
pulse width, TCLK_LMIN or TCLK_HMIN, is:
b----u---s-----f--r--e--1-q---u----e---n---c---y-- ^{+ tSU}
The maximum TCLK frequency is the least: 4 MHz or bus frequency ÷ 2.
PTD4/TBLCK is available as a general-purpose I/O pin or ADC channel
when not used as the TIMB clock input. When the PTD6/TACLK pin is
the TIMB clock input, it is an input regardless of the state of the DDRD6
bit in data direction register D.
TIMB Channel I/O
Pins
(PTF5/TBCH1–PTF4/
TBCH0)
Each channel I/O pin is programmable independently as an input
capture pin or an output compare pin. PTF4/TBCH0 and PTF5/TBCH1
can be configured as buffered output compare or buffered PWM pins.
15-timb
MOTOROLA
MC68HC08AZ60 — Rev 1.0
Timer Interface Module B (TIMB)
257
For More Information On This Product,
Go to: www.freescale.com