MC68HC08AZ60 Datasheet, PDF (428/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Appendix B: HC08AZ48 Memory Map
$FF00
↓
$FF7F
$FF80
$FF81
$FF82
↓
$FFCB
$FFCC
↓
$FFFF
Figure 1. Memory Map (Continued)
UNIMPLEMENTED (128 BYTES)
RESERVED
RESERVED
RESERVED (75 BYTES)
VECTORS (52BYTES)
$FF00
↓
$FF7F
$FF80
$FF81
$FF82
↓
$FFCB
$FFCC
↓
$FFFF
I/O Section
Addresses $0000–$003F, shown in Figure 2, contain most of the
control, status, and data registers. Additional I/O registers have these
addresses:
• $FE00 (SIM break status register, SBSR)
• $FE01 (SIM reset status register, SRSR)
• $FE03 (SIM break flag control register, SBFCR)
• $FE09 (configuration write-once register, CONFIG-2)
• $FE0C and $FE0D (break address registers, BRKH and BRKL)
• $FE0E (break status and control register, BRKSCR)
• $FE0F (LVI status register, LVISR)
• $FE18 (EEPROM non-volatile register, EENVR2)
• $FE19 (EEPROM control register, EECR2)
• $FE1B (EEPROM array configuration register, EEACR2)
• $FE1C (EEPROM non-volatile register, EENVR1)
• $FE1D (EEPROM control register, EECR1)
• $FE1F (EEPROM array configuration register, EEACR1)
• $FFFF (COP control register, COPCTL)
• Table 1 is a list of vector locations.
MC68HC08AZ60 — Rev 1.0
428
Appendix B: HC08AZ48 Memory Map
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