MC68HC08AZ60 Datasheet, PDF (340/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
MSCAN Controller (MSCAN08)
MSCAN08 Bus
Timing Register 0
Address: $0502
Bit 7
6
5
4
3
2
1
Read:
SJW1
Write:
SJW0
BRP5
BRP4
BRP3
BRP2
BRP1
Reset: 0
0
0
0
0
0
0
Figure 17. Bus Timing Register 0 (CBTR0)
Bit 0
BRP0
0
SJW1 and SJW0 — Synchronization Jump Width
The synchronization jump width (SJW) defines the maximum number
of time quanta (T_q) clock cycles by which a bit may be shortened, or
lengthened, to achieve resynchronization on data transitions on the
bus (see Table 6).
Table 6. Synchronization Jump Width
SJW1
0
0
1
1
SJW0
0
1
0
1
Synchronization Jump Width
1 T_q cycle
2 T_q cycle
3 T_q cycle
4 T_q cycle
BRP5–BRP0 — Baud Rate Prescaler
These bits determine the time quanta (T_q) clock, which is used to build
up the individual bit timing, according toTable 7.
Table 7. Baud Rate Prescaler
BRP5
0
0
0
0
:
:
1
BRP4
0
0
0
0
:
:
1
BRP3
0
0
0
0
:
:
1
BRP2
0
0
0
0
:
:
1
BRP1
0
0
1
1
:
:
1
BRP0
0
1
0
1
:
:
1
Prescaler Value (P)
1
2
3
4
:
:
64
NOTE: The CBTR0 register can be written only if the SFTRES bit in the
MSCAN08 module control register is set.
MC68HC08AZ60 — Rev 1.0
340
MSCAN Controller (MSCAN08)
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36-mscan
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