MC68HC08AZ60 Datasheet, PDF (121/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
CGM Registers
(PLLON = 0), selecting CGMVCLK requires two writes to the PLL control
register. See Base Clock Selector Circuit on page 115.
PCTL3–PCTL0 — Unimplemented
These bits provide no function and always read as logic 1s.
PLL Bandwidth
Control Register
The PLL bandwidth control register:
• Selects automatic or manual (software-controlled) bandwidth
control mode
• Indicates when the PLL is locked
• In automatic bandwidth control mode, indicates when the PLL is in
acquisition or tracking mode
• In manual operation, forces the PLL into acquisition or tracking
mode
Address: $001D
Bit 7
6
5
4
3
2
1
Bit 0
Read:
LOCK
0
0
0
0
AUTO
ACQ
XLD
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 5. PLL Bandwidth Control Register (PBWC)
17-cgm
MOTOROLA
MC68HC08AZ60 — Rev 1.0
Clock Generator Module (CGM)
121
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