MC68HC08AZ60 Datasheet, PDF (144/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Monitor ROM (MON)
Entering Monitor
Mode
Table 1 shows the pin conditions for entering monitor mode.
Table 1. Mode Selection
Mode
CGMOUT
Bus
Frequency
V_HI⁽¹⁾
V_HI⁽¹⁾
1 0 1 1 Monitor
1 0 1 0 Monitor
C-----G-----M----2-X----C----L---K--- _or C-----G-----M----2-V----C----L---K---
CGMXCLK
C-----G-----M--2---O----U-----T--
C-----G-----M--2---O----U-----T--
1. For V_HI, 5.0 Volt DC Electrical Characteristics on page 410, and
Maximum Ratings on page 408.
Enter monitor mode by either
• Executing a software interrupt instruction (SWI) or
• Applying a logic 0 and then a logic 1 to the RST pin.
Once out of reset, the MCU waits for the host to send eight security bytes
(see Security on page 151). After the security bytes, the MCU sends a
break signal (10 consecutive logic 0s) to the host computer, indicating
that it is ready to receive a command.
Monitor mode uses alternate vectors for reset, SWI, and break interrupt.
The alternate vectors are in the $FE page instead of the $FF page and
allow code execution from the internal monitor firmware instead of user
code. The COP module is disabled in monitor mode as long as V_HI (see
5.0 Volt DC Electrical Characteristics on page 410), is applied to
either the IRQ pin or the RESET pin. (See
System Integration Module (SIM) on page 83 for more information on
modes of operation).
NOTE:
Holding the PTC3 pin low when entering monitor mode causes a bypass
of a divide-by-two stage at the oscillator. The CGMOUT frequency is
equal to the CGMXCLK frequency, and the OSC1 input directly
generates internal bus clocks. In this case, the OSC1 signal must have
a 50% duty cycle at maximum bus frequency.
MC68HC08AZ60 — Rev 1.0
144
Monitor ROM (MON)
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4-mon
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