MC68HC08AZ60 Datasheet, PDF (266/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Timer Interface Module B (TIMB)
TIMB Channel
Registers
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at logic 0, setting the CHxMAX bit forces the
duty cycle of buffered and unbuffered PWM signals to 100%. As
Figure 8 shows, the CHxMAX bit takes effect in the cycle after it is set
or cleared. The output stays at the 100% duty cycle level until the
cycle after CHxMAX is cleared.
OVERFLOW
OVERFLOW
PERIOD
PTEx/TCHx
OVERFLOW
OVERFLOW
OVERFLOW
CHxMAX
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 8. CHxMAX Latency
These read/write registers contain the captured TIMB counter value of
the input capture function or the output compare value of the output
compare function. The state of the TIMB channel registers after reset is
unknown.
In input capture mode (MSxB–MSxA = 0:0), reading the high byte of the
TIMB channel x registers (TBCHxH) inhibits input captures until the low
byte (TBCHxL) is read.
In output compare mode (MSxB–MSxA ≠ 0:0), writing to the high byte of
the TIMB channel x registers (TBCHxH) inhibits output compares and
the CHxF bit until the low byte (TBCHxL) is written.
MC68HC08AZ60 — Rev 1.0
266
Timer Interface Module B (TIMB)
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