MC68HC08AZ60 Datasheet, PDF (192/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Serial Communications Interface Module (SCI)
• Framing error (FE) — The FE bit in SCS1 is set when a logic 0
occurs where the receiver expects a stop bit. The framing error
interrupt enable bit, FEIE, in SCC3 enables FE to generate SCI
error CPU interrupt requests.
• Parity error (PE) — The PE bit in SCS1 is set when the SCI
detects a parity error in incoming data. The parity error interrupt
enable bit, PEIE, in SCC3 enables PE to generate SCI error CPU
interrupt requests.
Low-Power Modes
The WAIT and STOP instructions put the MCU in low
power-consumption standby modes.
Wait Mode
The SCI module remains active in wait mode. Any enabled CPU
interrupt request from the SCI module can bring the MCU out of wait
mode.
If SCI module functions are not required during wait mode, reduce power
consumption by disabling the module before executing the WAIT
instruction.
Stop Mode
The SCI module is inactive in stop mode. The STOP instruction does not
affect SCI register states. SCI module operation resumes after the MCU
exits stop mode.
Because the internal clock is inactive during stop mode, entering stop
mode during an SCI transmission or reception results in invalid data.
MC68HC08AZ60 — Rev 1.0
192
Serial Communications Interface Module (SCI)
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