MC68HC08AZ60 Datasheet, PDF (260/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Timer Interface Module B (TIMB)
PS[2:0] — Prescaler Select Bits
These read/write bits select either the PTD4/TBLCK pin or one of the
seven prescaler outputs as the input to the TIMB counter as Table 1
shows. Reset clears the PS[2:0] bits.
PS[2:0]
000
001
010
011
100
101
110
111
Table 1. Prescaler Selection
TIMB Clock Source
Internal Bus Clock ÷1
Internal Bus Clock ÷ 2
Internal Bus Clock ÷ 4
Internal Bus Clock ÷ 8
Internal Bus Clock ÷ 16
Internal Bus Clock ÷ 32
Internal Bus Clock ÷ 64
PTD4/TBLCK
TIMB Counter
Registers
The two read-only TIMB counter registers contain the high and low bytes
of the value in the TIMB counter. Reading the high byte (TBCNTH)
latches the contents of the low byte (TBCNTL) into a buffer. Subsequent
reads of TBCNTH do not affect the latched TBCNTL value until TBCNTL
is read. Reset clears the TIMB counter registers. Setting the TIMB reset
bit (TRST) also clears the TIMB counter registers.
NOTE:
If TBCNTH is read during a break interrupt, be sure to unlatch TBCNTL
by reading TBCNTL before exiting the break interrupt. Otherwise,
TBCNTL retains the value latched during the break.
Register Name and Address TBCNTH — $0041
Bit 7
6
5
4
3
2
1
Read: BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9
Write: R
R
R
R
R
R
R
Reset: 0
0
0
0
0
0
0
Bit 0
BIT 8
R
0
Figure 5. TIMB Counter Registers (TBCNTH and TBCNTL)
MC68HC08AZ60 — Rev 1.0
260
Timer Interface Module B (TIMB)
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18-timb
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