MC68HC08AZ60 Datasheet, PDF (339/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
MSCAN Controller (MSCAN08)
Programmer’s Model of Control Registers
LOOPB — Loop Back Self-Test Mode
When this bit is set, the MSCAN08 performs an internal loop back
which can be used for self-test operation: the bit stream output of the
transmitter is fed back to the receiver internally. The RxCAN input pin
is ignored and the TxCAN output goes to the recessive state (logic
‘1’). The MSCAN08 behaves as it does normally when transmitting
and treats its own transmitted message as a message received from
a remote node. In this state the MSCAN08 ignores the bit sent during
the ACK slot of the CAN frame Acknowledge field to insure proper
reception of its own message. Both transmit and receive interrupt are
generated.
1 = Activate loop back self-test mode
0 = Normal operation
WUPM — Wakeup Mode
This flag defines whether the integrated low-pass filter is applied to
protect the MSCAN08 from spurious wakeups (see Programmable
Wakeup Function on page 324).
1 = MSCAN08 will wake up the CPU only in cases of a dominant
pulse on the bus which has a length of at least t_wup.
0 = MSCAN08 will wake up the CPU after any recessive to
dominant edge on the CAN bus.
CLKSRC — Clock Source
This flag defines which clock source the MSCAN08 module is driven
from (see Clock System on page 325).
1 = The MSCAN08 clock source is CGMOUT (see Figure 7).
0 = The MSCAN08 clock source is CGMXCLK/2 (see Figure 7).
NOTE: The CMCR1 register can be written only if the SFTRES bit in the
MSCAN08 module control register is set
35-mscan
MOTOROLA
MC68HC08AZ60 — Rev 1.0
MSCAN Controller (MSCAN08)
339
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