MC68HC08AZ60 Datasheet, PDF (114/452 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
f_BUS = ^f--V----^C_4---^L--^K--
Example: f_BUS= ^{3----2-----M4-----H----z--} = 8 MHz
6. If the calculated f_bus is not within the tolerance limits of your
application, select another f_BUSDES or another f_RCLK.
7. Using the value 4.9152 MHz for f_NOM, calculate the VCO linear
range multiplier, L. The linear range multiplier controls the
frequency range of the PLL.
L = round_ ^f-f-V-_N--^C-_O---^L-_M-^K--_
Example: L = _{4----.-9-3---1-2--5---M-2----HM----z-H-----z-} = 7
8. Calculate the VCO center-of-range frequency, f_VRS. The
center-of-range frequency is the midpoint between the minimum
and maximum frequencies attainable by the PLL.
NOTE:
f_VRS = L × f_NOM
Example: f_VRS = 7 × 4.9152 MHz = 34.4 MHz
For proper operation,f_VRS – f_VCLK
≤
f_NOM
-------₂---------
.
Exceeding the recommended maximum bus frequency or VCO
frequency can crash the MCU.
9. Program the PLL registers accordingly:
a. In the upper four bits of the PLL programming register (PPG),
program the binary equivalent of N.
b. In the lower four bits of the PLL programming register (PPG),
program the binary equivalent of L.
MC68HC08AZ60 — Rev 1.0
114
Clock Generator Module (CGM)
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10-cgm
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